MOVSS—Move or Merge Scalar Single-Precision Floating-Point Value

Instruction Operand Encoding

Description

Moves a scalar single-precision floating-point value from the source operand (second operand) to the destination operand (first operand). The source and destination operands can be XMM registers or 32-bit memory locations. This instruction can be used to move a single-precision floating-point value to and from the low doubleword of an XMM register and a 32-bit memory location, or to move a single-precision floating-point value between the low doublewords of two XMM registers. The instruction cannot be used to transfer data between memory locations.

Legacy version: When the source and destination operands are XMM registers, bits (MAX_VL-1:32) of the corre-sponding destination register are unmodified. When the source operand is a memory location and destination operand is an XMM registers, Bits (127:32) of the destination operand is cleared to all 0s, bits MAX_VL:128 of the destination operand remains unchanged.

VEX and EVEX encoded register-register syntax: Moves a scalar single-precision floating-point value from the second source operand (the third operand) to the low doubleword element of the destination operand (the first operand). Bits 127:32 of the destination operand are copied from the first source operand (the second operand). Bits (MAX_VL-1:128) of the corresponding destination register are zeroed.

VEX and EVEX encoded memory load syntax: When the source operand is a memory location and destination operand is an XMM registers, bits MAX_VL:32 of the destination operand is cleared to all 0s.

EVEX encoded versions: The low doubleword of the destination is updated according to the writemask.

Note: For memory store form instruction “VMOVSS m32, xmm1”, VEX.vvvv is reserved and must be 1111b other-wise instruction will #UD. For memory store form instruction “VMOVSS mv {k1}, xmm1”, EVEX.vvvv is reserved and must be 1111b otherwise instruction will #UD.

Software should ensure VMOVSS is encoded with VEX.L=0. Encoding VMOVSS with VEX.L=1 may encounter unpredictable behavior across different processor generations.

Operation

IF k1[0] or *no writemask*
    THEN
    DEST[31:0] (cid:197) SRC[31:0]
    ELSE
    IF *merging-masking*
        ; merging-masking
        THEN *DEST[31:0] remains unchanged*
        ELSE
        ; zeroing-masking
        THEN DEST[31:0] (cid:197) 0
    FI;
FI;
DEST[511:32] (cid:197) 0

IF k1[0] or *no writemask*
    THEN
    DEST[31:0] (cid:197) SRC[31:0]
    ELSE
    *DEST[31:0] remains unchanged*
    ; merging-masking
FI;

IF k1[0] or *no writemask*
    THEN
    DEST[31:0] (cid:197) SRC2[31:0]
    ELSE
    IF *merging-masking*
        ; merging-masking
        THEN *DEST[31:0] remains unchanged*
        ELSE
        ; zeroing-masking
        THEN DEST[31:0] (cid:197) 0
    FI;
FI;
DEST[127:32] (cid:197) SRC1[127:32]
DEST[MAX_VL-1:128] (cid:197) 0

DEST[31:0] (cid:197)SRC[31:0]
DEST[MAX_VL-1:32] (Unmodified)

DEST[31:0] (cid:197)SRC2[31:0]
DEST[127:32] (cid:197)SRC1[127:32]
DEST[MAX_VL-1:128] (cid:197)0

DEST[31:0] (cid:197)SRC2[31:0]
DEST[127:32] (cid:197)SRC1[127:32]
DEST[MAX_VL-1:128] (cid:197)0

DEST[31:0] (cid:197)SRC[31:0]
DEST[MAX_VL-1:32] (cid:197)0

DEST[31:0] (cid:197)SRC[31:0]

DEST[31:0] (cid:197)SRC[31:0]
DEST[127:32] (cid:197)0
DEST[MAX_VL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent

VMOVSS __m128 _mm_mask_load_ss(__m128 s, __mmask8 k, float * p);
VMOVSS __m128 _mm_maskz_load_ss( __mmask8 k, float * p);
VMOVSS __m128 _mm_mask_move_ss(__m128 sh, __mmask8 k, __m128 sl, __m128 a);
VMOVSS __m128 _mm_maskz_move_ss( __mmask8 k, __m128 s, __m128 a);
VMOVSS void _mm_mask_store_ss(float * p, __mmask8 k, __m128 a);
MOVSS __m128 _mm_load_ss(float * p)
MOVSS void_mm_store_ss(float * p, __m128 a)
MOVSS __m128 _mm_move_ss(__m128 a, __m128 b)

SIMD Floating-Point Exceptions

None

Other Exceptions

Non-EVEX-encoded instruction, see Exceptions Type 5; additionally