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PAND—Logical AND

Opcode/Instruction Op/En 64/32 bit Mode Support CPUID Feature Flag Description

0F DB /r1

PAND mm, mm/m64

 RM V/V MMX Bitwise AND mm/m64 and mm.

66 0F DB /r

PAND xmm1, xmm2/m128

 RM V/V SSE2 Bitwise AND of xmm2/m128 and xmm1.

VEX.NDS.128.66.0F.WIG DB /r

VPAND xmm1, xmm2, xmm3/m128

 RVM V/V AVX Bitwise AND of xmm3/m128 and xmm.

VEX.NDS.256.66.0F.WIG DB /r

VPAND ymm1, ymm2, ymm3/.m256

 RVM V/V AVX2 Bitwise AND of ymm2, and ymm3/m256 and store result in ymm1.

EVEX.NDS.128.66.0F.W0 DB /r

VPANDD xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst

 FV V/V AVX512VL AVX512F Bitwise AND of packed doubleword integers in xmm2 and xmm3/m128/m32bcst and store result in xmm1 using writemask k1.

EVEX.NDS.256.66.0F.W0 DB /r

VPANDD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst

 FV V/V AVX512VL AVX512F Bitwise AND of packed doubleword integers in ymm2 and ymm3/m256/m32bcst and store result in ymm1 using writemask k1.

EVEX.NDS.512.66.0F.W0 DB /r

VPANDD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst

 FV V/V AVX512F Bitwise AND of packed doubleword integers in zmm2 and zmm3/m512/m32bcst and store result in zmm1 using writemask k1.

EVEX.NDS.128.66.0F.W1 DB /r

VPANDQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst

 FV V/V AVX512VL AVX512F Bitwise AND of packed quadword integers in xmm2 and xmm3/m128/m64bcst and store result in xmm1 using writemask k1.

EVEX.NDS.256.66.0F.W1 DB /r

VPANDQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst

 FV V/V AVX512VL AVX512F Bitwise AND of packed quadword integers in ymm2 and ymm3/m256/m64bcst and store result in ymm1 using writemask k1.

EVEX.NDS.512.66.0F.W1 DB /r

VPANDQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst

 FV V/V AVX512F Bitwise AND of packed quadword integers in zmm2 and zmm3/m512/m64bcst and store result in zmm1 using writemask k1.

NOTES:

1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

Instruction Operand Encoding

Op/En Operand 1 Operand 2 Operand 3 Operand 4
RM ModRM:reg (r, w) ModRM:r/m (r) NA NA
RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA
FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA

Description

Performs a bitwise logical AND operation on the first source operand and second source operand and stores the result in the destination operand. Each bit of the result is set to 1 if the corresponding bits of the first and second operands are 1, otherwise it is set to 0.

In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).

Legacy SSE instructions: The source operand can be an MMX technology register or a 64-bit memory location. The destination operand can be an MMX technology register.

128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are unmodified.

EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1 at 32/64-bit granularity.

VEX.256 encoded versions: The first source operand is a YMM register. The second source operand is a YMM register or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256) of the corresponding ZMM register destination are zeroed.

VEX.128 encoded versions: The first source operand is an XMM register. The second source operand is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are zeroed.

Operation


PAND (64-bit operand)

DEST (cid:197) DEST AND SRC


PAND (128-bit Legacy SSE version)

DEST (cid:197) DEST AND SRC
DEST[VLMAX-1:128] (Unmodified)


VPAND (VEX.128 encoded version)

DEST (cid:197) SRC1 AND SRC2
DEST[VLMAX-1:128] (cid:197) 0


VPAND (VEX.256 encoded instruction)

DEST[255:0] (cid:197) (SRC1[255:0] AND SRC2[255:0])
DEST[VLMAX-1:256] (cid:197) 0


VPANDD (EVEX encoded versions)

(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j (cid:197) 0 TO KL-1
    i (cid:197) j * 32
    IF k1[j] OR *no writemask*
        THEN
        IF (EVEX.b = 1) AND (SRC2 *is memory*)
            THEN DEST[i+31:i] (cid:197) SRC1[i+31:i] BITWISE AND SRC2[31:0]
            ELSE DEST[i+31:i] (cid:197) SRC1[i+31:i] BITWISE AND SRC2[i+31:i]
        FI;
        ELSE
        IF *merging-masking*
            ; merging-masking
            THEN *DEST[i+31:i] remains unchanged*
            ELSE
            ; zeroing-masking
            DEST[i+31:i] (cid:197) 0
        FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] (cid:197) 0


VPANDQ (EVEX encoded versions)

(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j (cid:197) 0 TO KL-1
    i (cid:197) j * 64
    IF k1[j] OR *no writemask*
        THEN
        IF (EVEX.b = 1) AND (SRC2 *is memory*)
            THEN DEST[i+63:i] (cid:197) SRC1[i+63:i] BITWISE AND SRC2[63:0]
            ELSE DEST[i+63:i] (cid:197) SRC1[i+63:i] BITWISE AND SRC2[i+63:i]
        FI;
        ELSE
        IF *merging-masking*
            ; merging-masking
            THEN *DEST[i+63:i] remains unchanged*
            ELSE
            ; zeroing-masking
            DEST[i+63:i] (cid:197) 0
        FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] (cid:197) 0



Intel C/C++ Compiler Intrinsic Equivalent


VPANDD __m512i _mm512_and_epi32( __m512i a, __m512i b);
VPANDD __m512i _mm512_mask_and_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);
VPANDD __m512i _mm512_maskz_and_epi32( __mmask16 k, __m512i a, __m512i b);
VPANDQ __m512i _mm512_and_epi64( __m512i a, __m512i b);
VPANDQ __m512i _mm512_mask_and_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPANDQ __m512i _mm512_maskz_and_epi64( __mmask8 k, __m512i a, __m512i b);
VPANDND __m256i _mm256_mask_and_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPANDND __m256i _mm256_maskz_and_epi32( __mmask8 k, __m256i a, __m256i b);
VPANDND __m128i _mm_mask_and_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPANDND __m128i _mm_maskz_and_epi32( __mmask8 k, __m128i a, __m128i b);
VPANDNQ __m256i _mm256_mask_and_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPANDNQ __m256i _mm256_maskz_and_epi64( __mmask8 k, __m256i a, __m256i b);
VPANDNQ __m128i _mm_mask_and_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPANDNQ __m128i _mm_maskz_and_epi64( __mmask8 k, __m128i a, __m128i b);
PAND:
         __m64 _mm_and_si64 (__m64 m1, __m64 m2)
(V)PAND:__m128i _mm_and_si128 ( __m128i a, __m128i b)
VPAND:
              __m256i _mm256_and_si256 ( __m256i a, __m256i b)



Flags Affected


None.


Numeric Exceptions


None.


Other Exceptions


Non-EVEX-encoded instruction, see Exceptions Type 4.


EVEX-encoded instruction, see Exceptions Type E4.