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VDBPSADBW—Double Block Packed Sum-Absolute-Differences (SAD) on Unsigned Bytes

Opcode/Instruction Op /En 64/32 bit Mode Support CPUID Feature Flag Description

EVEX.NDS.128.66.0F3A.W0 42 /r ib

VDBPSADBW xmm1 {k1}{z}, xmm2, xmm3/m128, imm8

 FVM V/V

AVX512VL

AVX512BW

 Compute packed SAD word results of unsigned bytes in dword block from xmm2 with unsigned bytes of dword blocks transformed from xmm3/m128 using the shuffle controls in imm8. Results are written to xmm1 under the writemask k1.

EVEX.NDS.256.66.0F3A.W0 42 /r ib

VDBPSADBW ymm1 {k1}{z}, ymm2, ymm3/m256, imm8

 FVM V/V

AVX512VL

AVX512BW

 Compute packed SAD word results of unsigned bytes in dword block from ymm2 with unsigned bytes of dword blocks transformed from ymm3/m256 using the shuffle controls in imm8. Results are written to ymm1 under the writemask k1.

EVEX.NDS.512.66.0F3A.W0 42 /r ib

VDBPSADBW zmm1 {k1}{z}, zmm2, zmm3/m512, imm8

 FVM V/V AVX512BW Compute packed SAD word results of unsigned bytes in dword block from zmm2 with unsigned bytes of dword blocks transformed from zmm3/m512 using the shuffle controls in imm8. Results are written to zmm1 under the writemask k1.

Instruction Operand Encoding

Op/En Operand 1 Operand 2 Operand 3 Operand 4
FVM ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) Imm8

Description

Compute packed SAD (sum of absolute differences) word results of unsigned bytes from two 32-bit dword elements. Packed SAD word results are calculated in multiples of qword superblocks, producing 4 SAD word results in each 64-bit superblock of the destination register.

Within each super block of packed word results, the SAD results from two 32-bit dword elements are calculated as follows:

The first source operand is a ZMM/YMM/XMM register. The second source operand is a ZMM/YMM/XMM register, or a 512/256/128-bit memory location. The destination operand is conditionally updated based on writemask k1 at 16-bit word granularity.

127+128*n

128-bit Lane of Src2

95+128*n

imm8 shuffle control

63+128*n

0

31+128*n

00B: DW0

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01B: DW1

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10B: DW2 11B: DW3

 128*n

127+128*n

128-bit Lane of Tmp1

24

32

_

abs

+

47

63

_

abs

95+128*n

Tmp1 sliding dword

Src1 stationary dword 1

16

32

_

abs

+

63+128*n

31

23

_

abs

Tmp1 sliding dword

Src1 stationary dword 1

31+128*n

Tmp1 qword superblock

8

0

_

abs

+

15

15

_

abs

+

128*n

Tmp1 sliding dword

Src1 stationary dword 0

0

Tmp1 sliding dword

0

Src1 stationary dword 0

_

abs

63

Destination qword superblock

 47 31 15 0
DW3 DW2 DW1 DW0

Figure 5-8. 64-bit Super Block of SAD Operation in VDBPSADBW

Operation


VDBPSADBW (EVEX encoded versions)

(KL, VL) = (8, 128), (16, 256), (32, 512)
Selection of quadruplets:
FOR I = 0 to VL step 128
    TMP1[I+31:I] (cid:197) select (SRC2[I+127: I], imm8[1:0])
    TMP1[I+63: I+32] (cid:197) select (SRC2[I+127: I], imm8[3:2])
    TMP1[I+95: I+64] (cid:197) select (SRC2[I+127: I], imm8[5:4])
    TMP1[I+127: I+96](cid:197) select (SRC2[I+127: I], imm8[7:6])
    END FOR
    SAD of quadruplets:
    FOR I =0 to VL step 64
        TMP_DEST[I+15:I] (cid:197) ABS(SRC1[I+7: I] - TMP1[I+7: I]) +
        ABS(SRC1[I+15: I+8]- TMP1[I+15: I+8]) +
        ABS(SRC1[I+23: I+16]- TMP1[I+23: I+16]) +
        ABS(SRC1[I+31: I+24]- TMP1[I+31: I+24])
        TMP_DEST[I+31: I+16] (cid:197)ABS(SRC1[I+7: I] - TMP1[I+15: I+8]) +
        ABS(SRC1[I+15: I+8]- TMP1[I+23: I+16]) +
        ABS(SRC1[I+23: I+16]- TMP1[I+31: I+24]) +
        ABS(SRC1[I+31: I+24]- TMP1[I+39: I+32])
        TMP_DEST[I+47: I+32] (cid:197)ABS(SRC1[I+39: I+32] - TMP1[I+23: I+16]) +
        ABS(SRC1[I+47: I+40]- TMP1[I+31: I+24]) +
        ABS(SRC1[I+55: I+48]- TMP1[I+39: I+32]) +
        ABS(SRC1[I+63: I+56]- TMP1[I+47: I+40])
        TMP_DEST[I+63: I+48] (cid:197)ABS(SRC1[I+39: I+32] - TMP1[I+31: I+24]) +
        ABS(SRC1[I+47: I+40] - TMP1[I+39: I+32]) +
        ABS(SRC1[I+55: I+48] - TMP1[I+47: I+40]) +
        ABS(SRC1[I+63: I+56] - TMP1[I+55: I+48])
    ENDFOR
    FOR j (cid:197) 0 TO KL-1
        i (cid:197)  j * 16
        IF k1[j] OR *no writemask*
            THEN DEST[i+15:i] (cid:197) TMP_DEST[i+15:i]
            ELSE
            IF *merging-masking*
                ; merging-masking
                THEN *DEST[i+15:i] remains unchanged*
                ELSE
                ; zeroing-masking
                DEST[i+15:i] (cid:197) 0
            FI
        FI;
    ENDFOR
    DEST[MAX_VL-1:VL] (cid:197) 0
    


Intel C/C++ Compiler Intrinsic Equivalent


VDBPSADBW __m512i _mm512_dbsad_epu8(__m512i a, __m512i b);
VDBPSADBW __m512i _mm512_mask_dbsad_epu8(__m512i s, __mmask32 m, __m512i a, __m512i b);
VDBPSADBW __m512i _mm512_maskz_dbsad_epu8(__mmask32 m, __m512i a, __m512i b);
VDBPSADBW __m256i _mm256_dbsad_epu8(__m256i a, __m256i b);
VDBPSADBW __m256i _mm256_mask_dbsad_epu8(__m256i s, __mmask16 m, __m256i a, __m256i b);
VDBPSADBW __m256i _mm256_maskz_dbsad_epu8(__mmask16 m, __m256i a, __m256i b);
VDBPSADBW __m128i _mm_dbsad_epu8(__m128i a, __m128i b);
VDBPSADBW __m128i _mm_mask_dbsad_epu8(__m128i s, __mmask8 m, __m128i a, __m128i b);
VDBPSADBW __m128i _mm_maskz_dbsad_epu8(__mmask8 m, __m128i a, __m128i b);



SIMD Floating-Point Exceptions


None


Other Exceptions


See Exceptions Type E4NF.nb.