VGETEXPPD—Convert Exponents of Packed DP FP Values to DP FP Values

Instruction Operand Encoding

Description

Extracts the biased exponents from the normalized DP FP representation of each qword data element of the source operand (the second operand) as unbiased signed integer value, or convert the denormal representation of input data to unbiased negative integer values. Each integer value of the unbiased exponent is converted to double-precision FP value and written to the corresponding qword elements of the destination operand (the first operand) as DP FP numbers.

The destination operand is a ZMM/YMM/XMM register and updated under the writemask. The source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 64-bit memory location.

EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

Each GETEXP operation converts the exponent value into a FP number (permitting input value in denormal repre-sentation). Special cases of input values are listed in Table 5-7.

The formula is:

GETEXP(x) = floor(log₂(|x|))

Notation floor(x) stands for the greatest integer not exceeding real number x.

Table 5-7. VGETEXPPD/SD Special Cases

Operation

NormalizeExpTinyDPFP(SRC[63:0])
{
// Jbit is the hidden integral bit of a FP number. In case of denormal number it has the value of ZERO.
Src.Jbit (cid:197) 0;
Dst.exp (cid:197) 1;
Dst.fraction (cid:197) SRC[51:0];
WHILE(Src.Jbit = 0)
{
Src.Jbit (cid:197) Dst.fraction[51];
// Get the fraction MSB
Dst.fraction (cid:197) Dst.fraction << 1 ;
// One bit shift left
Dst.exp-- ;
// Decrement the exponent
}
Dst.fraction (cid:197) 0;
// zero out fraction bits
Dst.sign (cid:197) 1;
// Return negative sign
TMP[63:0] (cid:197) MXCSR.DAZ? 0 : (Dst.sign << 63) OR (Dst.exp << 52) OR (Dst.fraction) ;
Return (TMP[63:0]);
}
ConvertExpDPFP(SRC[63:0])
{
Src.sign (cid:197) 0;
// Zero out sign bit
Src.exp (cid:197) SRC[62:52];
Src.fraction (cid:197) SRC[51:0];
// Check for NaN
IF (SRC = NaN)
    {
    IF ( SRC = SNAN ) SET IE;
        Return QNAN(SRC);
        }
        // Check for +INF
        IF (SRC = +INF) Return (SRC);
            // check if zero operand
            IF ((Src.exp = 0) AND ((Src.fraction = 0) OR (MXCSR.DAZ = 1))) Return (-INF);
                }
                ELSE
                // check if denormal operand (notice that MXCSR.DAZ = 0)
                {
                IF ((Src.exp = 0) AND (Src.fraction != 0))
                    {
                    TMP[63:0] (cid:197) NormalizeExpTinyDPFP(SRC[63:0]) ;
                    // Get Normalized Exponent
                    Set #DE
                    }
                    ELSE
                    // exponent value is correct
                    {
                    Dst.fraction (cid:197) 0;
                    // zero out fraction bits
                    TMP[63:0] (cid:197) (Src.sign << 63) OR (Src.exp << 52) OR (Src.fraction) ;
                    }
                    TMP (cid:197) SAR(TMP, 52) ;
                    // Shift Arithmetic Right
                    TMP (cid:197) TMP – 1023;
                    // Subtract Bias
                    Return CvtI2D(TMP) ;
                    // Convert INT to Double-Precision FP number
                    }
                    }

(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j (cid:197) 0 TO KL-1
    i (cid:197) j * 64
    IF k1[j] OR *no writemask*
        THEN
        IF (EVEX.b = 1) AND (SRC *is memory*)
            THEN
            DEST[i+63:i] (cid:197)
            ConvertExpDPFP(SRC[63:0])
            ELSE
            DEST[i+63:i] (cid:197)
            ConvertExpDPFP(SRC[i+63:i])
        FI;
        ELSE
        IF *merging-masking*
            ; merging-masking
            THEN *DEST[i+63:i] remains unchanged*
            ELSE
            ; zeroing-masking
            DEST[i+63:i] (cid:197) 0
        FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] (cid:197) 0

Intel C/C++ Compiler Intrinsic Equivalent

VGETEXPPD __m512d _mm512_getexp_pd(__m512d a);
VGETEXPPD __m512d _mm512_mask_getexp_pd(__m512d s, __mmask8 k, __m512d a);
VGETEXPPD __m512d _mm512_maskz_getexp_pd( __mmask8 k, __m512d a);
VGETEXPPD __m512d _mm512_getexp_round_pd(__m512d a, int sae);
VGETEXPPD __m512d _mm512_mask_getexp_round_pd(__m512d s, __mmask8 k, __m512d a, int sae);
VGETEXPPD __m512d _mm512_maskz_getexp_round_pd( __mmask8 k, __m512d a, int sae);
VGETEXPPD __m256d _mm256_getexp_pd(__m256d a);
VGETEXPPD __m256d _mm256_mask_getexp_pd(__m256d s, __mmask8 k, __m256d a);
VGETEXPPD __m256d _mm256_maskz_getexp_pd( __mmask8 k, __m256d a);
VGETEXPPD __m128d _mm_getexp_pd(__m128d a);
VGETEXPPD __m128d _mm_mask_getexp_pd(__m128d s, __mmask8 k, __m128d a);
VGETEXPPD __m128d _mm_maskz_getexp_pd( __mmask8 k, __m128d a);

SIMD Floating-Point Exceptions

Invalid, Denormal

Other Exceptions

See Exceptions Type E2.