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VPCOMPRESSQ—Store Sparse Packed Quadword Integer Values into Dense Memory/Register

Opcode/Instruction Op/En 64/32 bit Mode Support CPUID Feature Flag Description

EVEX.128.66.0F38.W1 8B /r

VPCOMPRESSQ xmm1/m128 {k1}{z}, xmm2

 T1S V/V

AVX512VL

AVX512F

 Compress packed quadword integer values from xmm2 to xmm1/m128 using controlmask k1.

EVEX.256.66.0F38.W1 8B /r

VPCOMPRESSQ ymm1/m256 {k1}{z}, ymm2

 T1S V/V

AVX512VL

AVX512F

 Compress packed quadword integer values from ymm2 to ymm1/m256 using controlmask k1.

EVEX.512.66.0F38.W1 8B /r

VPCOMPRESSQ zmm1/m512 {k1}{z}, zmm2

 T1S V/V AVX512F Compress packed quadword integer values from zmm2 to zmm1/m512 using controlmask k1.

Instruction Operand Encoding

Op/En Operand 1 Operand 2 Operand 3 Operand 4
T1S ModRM:r/m (w) ModRM:reg (r) NA NA

Description

Compress (stores) up to 8/4/2 quadword integer values from the source operand (second operand) to the destina-tion operand (first operand). The source operand is a ZMM/YMM/XMM register, the destination operand can be a ZMM/YMM/XMM register or a 512/256/128-bit memory location.

The opmask register k1 selects the active elements (partial vector or possibly non-contiguous if less than 8 active elements) from the source operand to compress into a contiguous vector. The contiguous vector is written to the destination starting from the low element of the destination operand.

Memory destination version: Only the contiguous vector is written to the destination memory location. EVEX.z must be zero.

Register destination version: If the vector length of the contiguous vector is less than that of the input vector in the source operand, the upper bits of the destination register are unmodified if EVEX.z is not set, otherwise the upper bits are zeroed.

Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

Note that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element instead of the size of the full vector.

Operation


VPCOMPRESSQ (EVEX encoded versions) store form

(KL, VL) = (2, 128), (4, 256), (8, 512)
SIZE (cid:197)(cid:3)64
k (cid:197) 0
FOR j (cid:197) 0 TO KL-1
    i (cid:197) j * 64
    IF k1[j] OR *no controlmask*
        THEN
        DEST[k+SIZE-1:k](cid:197) SRC[i+63:i]
        k (cid:197) k + SIZE
    FI;
    ENFOR


VPCOMPRESSQ (EVEX encoded versions) reg-reg form

(KL, VL) = (2, 128), (4, 256), (8, 512)
SIZE (cid:197)(cid:3)64
k (cid:197) 0
FOR j (cid:197) 0 TO KL-1
    i (cid:197) j * 64
    IF k1[j] OR *no controlmask*
        THEN
        DEST[k+SIZE-1:k](cid:197) SRC[i+63:i]
        k (cid:197) k + SIZE
    FI;
ENDFOR IF *merging-masking*
THEN *DEST[VL-1:k] remains unchanged* ELSE DEST[VL-1:k] ← 0
FI
DEST[MAX_VL-1:VL] (cid:197) 0



Intel C/C++ Compiler Intrinsic Equivalent


VPCOMPRESSQ __m512i _mm512_mask_compress_epi64(__m512i s, __mmask8 c, __m512i a);
VPCOMPRESSQ __m512i _mm512_maskz_compress_epi64( __mmask8 c, __m512i a);
VPCOMPRESSQ void _mm512_mask_compressstoreu_epi64(void * a, __mmask8 c, __m512i s);
VPCOMPRESSQ __m256i _mm256_mask_compress_epi64(__m256i s, __mmask8 c, __m256i a);
VPCOMPRESSQ __m256i _mm256_maskz_compress_epi64( __mmask8 c, __m256i a);
VPCOMPRESSQ void _mm256_mask_compressstoreu_epi64(void * a, __mmask8 c, __m256i s);
VPCOMPRESSQ __m128i _mm_mask_compress_epi64(__m128i s, __mmask8 c, __m128i a);
VPCOMPRESSQ __m128i _mm_maskz_compress_epi64( __mmask8 c, __m128i a);
VPCOMPRESSQ void _mm_mask_compressstoreu_epi64(void * a, __mmask8 c, __m128i s);



SIMD Floating-Point Exceptions


None


Other Exceptions


EVEX-encoded instruction, see Exceptions Type E4.nb.